Method for implementing overlay-based modification of VLSI design layout
US7490308B2 · kind B2 · utility
4Cited by
5References
6Claims
0Family size
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Key dates
| Filing date | Mar 31, 2006 |
| Grant date | Feb 10, 2009 |
| Priority date | — |
| Expiry date | Oct 1, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of modifying a VLSI layout for performance optimization includes defining a revised set of ground rules for a plurality of original device shapes to be modified and flattening the plurality of original device shapes to a prime cell. A layout optimization operation is performed on the flattened device shapes, based on the revised set of ground rules, so as to create a plurality of revised device shapes. An overlay cell is then created from a difference between the revised device shapes and the original device shapes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.