Partition-based incremental implementation flow for use with a programmable logic device
US7490312B1 · kind B1 · utility
8Cited by
8References
16Claims
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Key dates
| Filing date | Aug 8, 2006 |
| Grant date | Feb 10, 2009 |
| Priority date | — |
| Expiry date | Jan 30, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of incremental flow for a programmable logic device can include identifying elements of a hardware description language representation of a circuit design and specifying a hierarchy of partitions for selected ones of the elements. Portions of implementation data from a prior implementation flow for the circuit design can be associated with corresponding partitions. Selected portions of the implementation data from the prior implementation flow for at least one partition can be re-used during an incremental flow of the circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.