Method of forming isolation structures in a semiconductor manufacturing process
US7491621B2 · kind B2 · utility
1Cited by
7References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2006 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | Jan 30, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming shallow trench isolation structures is disclosed. The methods include providing a substrate having an upper surface and having an opening extending down from said upper surface, providing a first dielectric layer over at least a portion of the upper surface of the substrate and filling the opening, providing a second dielectric layer over the first dielectric layer, and removing portions of the first and second dielectric layers, wherein the first dielectric layer has a higher index of refraction than the second dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.