Nitride-based semiconductor device of reduced current leakage
US7491983B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2006 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | Aug 12, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high electron mobility transistor is disclosed which has a double-layered main semiconductor region formed on a silicon substrate via a multilayered buffer region. The multilayered buffer region is in the form of alternations of an aluminum nitride layer and a gallium nitride layer. The main semiconductor region, buffer region, and part of the substrate taper as they extend away from the rest of the substrate, providing slanting side surfaces. An electroconductive antileakage overlay covers these side surfaces via an electrically insulating overlay. Electrically coupled to the silicon substrate via a contact electrode, the antileakage overlay serves for reduction of current leakage along the side surfaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.