Semiconductor circuit
US7492341B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2004 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | Apr 1, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G3/3677
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor circuit with the reduced scale of circuitry and a semiconductor integrated circuit chip which is obtained by integrating the semiconductor circuit and enables chip size reduction are provided. For this purpose, a two-decode method is used. The method uses: a pre-decode circuit comprising a first decoder of the preceding stage which decodes an arbitrary bit of an address signal of eight bits and a second decoder of the preceding stage which decodes the remaining bits; level conversion circuits which shift the output of the pre-decode circuit; and post-decode circuits which decode the decode outputs of the decoders in the pre-decode circuit, level-converted through the level conversion circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.