Systems and methods for reducing simultaneous switching noise in an integrated circuit
US7492570B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 13, 2005 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | Jun 6, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10734
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Systems and methods for reducing switching noise in an integrated circuit. In one embodiment, decoupling capacitors are connected to the integrated circuit from the underside of the substrate on which the integrated circuit die is manufactured. The decoupling capacitors are positioned with a higher concentration in the “hot spot” areas of the integrated circuit instead of being evenly distributed. In one embodiment, the decoupling capacitors and the corresponding hole(s) in a circuit board on which the integrated circuit is mounted are positioned so that the circuit board provides support for the central portion of the integrated circuit and thereby prevents the integrated circuit from flexing away from the heat sink/spreader. In one embodiment, the concentration of vias connecting the different ground planes and/or power planes within the integrated circuit is higher in hot spots than in other areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.