Pseudo-random bit sequence (PRBS) synchronization for interconnects with dual-tap scrambling devices and methods
US7492807B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2008 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | Apr 7, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4234
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for synchronizing interconnects in a link system according to various embodiments can include receiving input data at a transmit side, the transmit side including at least one pseudo-random bit sequence scrambler; scrambling the input data at the transmit side via the pseudo-random bit scrambler with dual tap sequences resulting in scrambled data; transmitting the scrambled data with the dual tap sequences along all lanes of a plurality of lanes to a receive side via a bus interconnecting the plurality of lanes, the receive side including at least one pseudo-random bit sequence descrambler; synchronizing the at least one pseudo-random bit sequence scrambler to the at least one pseudo-random bit sequence descrambler; using an edge detection or transition detection device for synchronization of the descrambler to the scrambler; and de-scrambling the transmitted scrambled data at the receive side resulting in the input data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.