Peter Buchmann
21Patents
13h-index
29Co-inventors
81Inventor score
Filing activity: Mar 17, 1987 → Nov 19, 2014
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5177031A | Method of passivating etched mirror facets of semiconductor laser diodes | Emerging Cross-Sectional Technologies | 152 | Expired |
| US5376587A | Method for making cooling structures for directly cooling an active layer of a semiconductor chip | Electricity | 93 | Expired |
| US4803181A | Process for forming sub-micrometer patterns using silylation of resist side walls | Emerging Cross-Sectional Technologies | 88 | Expired |
| US5319725A | Bilithic composite for optoelectronic integration | Electricity | 55 | Expired |
| US5032879A | Integrated semiconductor diode laser and photodiode structure | Electricity | 53 | Expired |
| US5287001A | Cooling structures and package modules for semiconductors | Electricity | 49 | Expired |
| US8139430B2 | Power-on initialization and test for a cascade interconnect memory system | Emerging Cross-Sectional Technologies | 39 | Active |
| US5032219A | Method for improving the planarity of etched mirror facets | Electricity | 37 | Expired |
| US6768716B1 | Load balancing system, apparatus and method | Electricity | 37 | Expired |
| US4732871A | Process for producing undercut dummy gate mask profiles for MESFETs | Electricity | 35 | Expired |
| US5103493A | Improved planar etched mirror facets | Electricity | 20 | Expired |
| US7492807B1 | Pseudo-random bit sequence (PRBS) synchronization for interconnects with dual-tap scrambling devices and methods | Physics | 17 | Active |
| US7240249B2 | Circuit for bit skew suppression in high speed multichannel data transmission | Electricity | 13 | Expired |
| US7684534B2 | Method and apparatus for handling of clock information in serial link ports | Electricity | 10 | Active |
| US7511442B2 | Linear drive device | Physics | 10 | Active |
| US8516338B2 | Error correcting code protected quasi-static bit communication on a high-speed bus | Physics | 8 | Active |
| US8149979B2 | Method and apparatus for handling of clock information in serial link ports | Electricity | 6 | Active |
| US8234540B2 | Error correcting code protected quasi-static bit communication on a high-speed bus | Physics | 5 | Active |
| US9252785B2 | Clock recovery for a data receiving unit | Electricity | 1 | Active |
| US9143045B2 | Switched-mode power supply using ac-dc conversion having inverted control | Emerging Cross-Sectional Technologies | 1 | Active |
| US8645620B2 | Apparatus and method for accessing a memory device | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.