PMA RX in coarse loop for high speed sampling
US7493095B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2007 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | May 1, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. A transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.