Integrated circuit analysis system and method using model checking
US7493247B2 · kind B2 · utility
26Cited by
2References
18Claims
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Key dates
| Filing date | Dec 7, 2005 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | Nov 2, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and system for verifying an integrated circuit using a Model Checker at post-silicon time to improve post-silicon assertion-based verification. A dialog is established between the Model Checker and a fabricated integrated circuit under test (ICUT), to increase the state space which is explored. ICUT-based traces from the integrated current are generated, in part based on initial states and assertions provided by the Model Checker or by a user. The Model Checker verifies the integrated circuit by generating Model Checker-based traces from basic logic, which are reproductions of the ICUT-based traces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.