Apparatus and method for synchronizing multiple threads in an out-of-order microprocessor
US7493615B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2003 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | Sep 15, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention generally relates to synchronization of multiple threads in an out-of-order microprocessor utilizing the insertion of a trap. In one embodiment, while synchronizing multiple running threads, an instruction within a first running thread is identified. Upon identification of this instruction, a trap is inserted into a second running thread. All instructions within the instructional pipeline that are scheduled for execution prior to this trapped instruction must retire before the subsequent execution of the synchronizing instruction. Following the execution of the synchronizing instruction, all instructions within the instruction pipeline slated for execution after the trapped instruction in the remaining threads are flushed and refetched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.