Patent · US Active

Top contact alignment in semiconductor devices

US7494825B2 · kind B2 · utility

2Cited by
1References
17Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJan 3, 2007
Grant dateFeb 24, 2009
Priority date
Expiry dateJan 3, 2027

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY10S438/975

Abstract

According to an example embodiment, a semiconductor device includes a lower electrode (316) disposed on an oxide layer (302), an upper electrode (320) disposed on the lower electrode, a dielectric pattern (322) disposed on the oxide layer and surrounding the upper electrode, the upper electrode protruding above an upper surface of the dielectric pattern, and a contact pattern (328) that is contiguous with the upper electrode and the dielectric pattern.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.