Semiconductor device having metal gate patterns and related method of manufacture
US7494859B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2006 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Jun 1, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprising a semiconductor substrate having a first impurity region and a second impurity region, a first gate pattern formed on the first impurity region, and a second gate pattern formed on the second impurity region is disclosed. The first gate pattern comprises a first gate insulation layer pattern, a metal layer pattern having a first thickness, and a first polysilicon layer pattern. The second gate pattern comprises a second gate insulation layer pattern, a metal silicide layer pattern having a second thickness smaller than the first thickness, and a second polysilicon layer pattern. The metal silicide layer pattern is formed from a material substantially the same as the material from which the metal layer pattern is formed. A method for manufacturing the semiconductor device is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.