Fabrication method of metal oxide semiconductor transistor
US7494865B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2006 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Nov 29, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/027
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of metal oxide semiconductor transistor is provided. A substrate is provided. A source/drain extension region is formed in the substrate. A pad material layer with low dielectric constant is formed on the substrate. A trench is formed in the substrate and the pad material layer. A gate dielectric layer is formed on the surface of the substrate in the trench. A stacked gate structure is formed in the trench, wherein the top surface of a conductive layer of the stacked gate structure is higher than the surface of the pad material layer. A spacer material layer is formed conformably on the substrate. Portions of the spacer material layer and the pad material layer are removed so as to form a pair of first spacers and a pair of pad blocks. A source/drain is formed on the substrate beside the stacked gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.