Method for post lithographic critical dimension shrinking using thermal reflow process
US7494919B2 · kind B2 · utility
3Cited by
7References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2005 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Feb 25, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for reducing the size of a patterned semiconductor feature includes forming a first layer over a substrate to be patterned, and forming a photoresist layer over the first layer. The photoresist layer is patterned so as to expose portions of the first layer, and the exposed portions of the first layer are removed in a manner so as to create an undercut region beneath the patterned photoresist layer. The patterned photoresist layer is reflowed so as to cause reflowed portions of the patterned photoresist layer to occupy at least a portion of the undercut region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.