Method for the formation of an integrated electronic circuit having a closed cavity
US7494932B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 26, 2006 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Feb 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated electronic circuit includes a cavity buried in a substrate. A surface of the substrate has a depression aligned above the buried cavity. The depression is filled with a material selected so that reflection of a lithography radiation on the substrate surface is attenuated. A resist layer is deposited on the circuit and then exposed to the radiation so that those resist portions which are located above the depression and those located away from the depression receive amounts of radiation that are below and above, respectively, the development threshold of the resist. An etching mask is therefore obtained on the circuit, which is aligned with respect to the cavity and its associated surface depression.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.