Test structure and method for detecting and studying crystal lattice dislocation defects in integrated circuit devices
US7495254B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2005 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Dec 22, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/32
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A test structure (200, 200′) having an array (224) of test devices (220) for detecting and studying defects that can occur in an integrated circuit device, e.g., a transistor (144), due to the relative positioning of one component (100) of the device with respect to another component (108) of the device. The test devices in the array are of a like kind, but vary in their configuration. The differences in the configurations are predetermined and selected with the intent of forcing defects to occur within at least some of the test devices. During testing, the responses of the test devices are sensed so as to determine whether or not a defect has occurred in any one or more of the test devices. If a defective test device is detected, the corresponding wafer (204) may be subjected to physical failure analysis for yield learning.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.