Frequency multiplying delay-locked loop
US7495489B2 · kind B2 · utility
4Cited by
9References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2006 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Mar 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Frequency multiplying delay-locked loop techniques are described in which a plurality of phase shifted signals are generated utilizing a delay-locked loop circuit having a clock multiplication, the phase shifted signals having increased frequency relative to the incoming signal. The phase-shifted signals being generated by the delay-locked loop in order to position the clock to an optimal detection point of incoming data signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.