Inverter based duty cycle correction apparatuses and systems
US7495491B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 28, 2007 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Apr 30, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356104
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Apparatuses, circuits, and methods to reduce duty cycle errors are disclosed. Embodiments generally comprise buffer circuits coupled with error detection circuits and correction feedback circuits that sense duty cycles errors in output signals from the buffer circuits, generate error signals, and couple the error signals back to the inputs to correct or reduce the duty cycle errors. The error circuits may comprise active low pass filters in various embodiments, while amplifiers generally comprise inverter buffers or other simple buffers which alter or affect the input signals to the buffer circuits in order to reduce the duty cycle errors. In many system and apparatus embodiments, the error circuits comprise a resistor-capacitor circuit coupled with an inverter buffer. The error detection circuits generally function as active low pass filters and generate error signals for the feedback circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.