Dynamic latch state saving device and protocol
US7495492B2 · kind B2 · utility
0Cited by
9References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2006 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Jun 7, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C14/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention comprises a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.