Program and erase methods and structures for byte-alterable flash memory
US7495958B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 6, 2006 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Mar 17, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array of flash memory cells arranged in a plurality of rows and a plurality of columns includes a first row comprising a plurality of units. Each unit includes a plurality of flash memory cells, an erase-gate line connecting erase-gates of all flash memory cells in the first row, a source line connecting source nodes of all flash memory cells in the first row, a word line connecting word-line nodes of all flash memory cells in the first row, and a local control-gate (CG) line connecting control-gates of flash memory cells only in the unit, wherein each local CG line is disconnected from remaining local CG lines in the first row. The array further includes bit-lines each connecting bit-line nodes of flash memory cells in a same column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.