Patent · US Active

Semiconductor arrangement

US7498194B2 · kind B2 · utility

0Cited by

11References

15Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Nikolaus Bott · Villach, AT
Oliver Haeberlen · Villach, AT
Manfred Kotek · Villach, AT
Joost Larik · Poing, DE
Josef Maerz · Oberhaching, DE
Ralf Otremba · Kaufbeuren, DE

Key dates

Filing date	Apr 11, 2007
Grant date	Mar 3, 2009
Priority date	—
Expiry date	Apr 27, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/181
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.