Methods of manufacturing semiconductor memory devices with unit cells having charge trapping layers
US7498217B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2007 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Sep 17, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76229
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of manufacturing a semiconductor device such as a SONOS type semiconductor device, a trench is formed on a substrate. An isolation layer protruding from the substrate is formed to fill the trench. After a first layer is formed on the substrate, a preliminary second layer pattern is formed on the first layer. The preliminary second layer pattern has an upper face substantially lower than or substantially equal to an upper face of the isolation layer. A third layer is formed on the preliminary second layer and the isolation layer. A fourth layer is formed on the third layer. The fourth layer, the third layer, the preliminary second layer pattern and the first layer are partially etched to form a gate structure on the substrate. Source/drain regions are formed at portions of the substrate adjacent to the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.