Silicon wafer thinning end point method
US7498236B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2006 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Mar 12, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/78
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are a method of and system for fabricating a semiconductor wafer. The method comprises the steps of providing a silicon wafer having a front side an a back side, building an integrated circuit on the front side of the wafer, and thereafter removing substrate from the back side of the silicon wafer. The building step includes the steps of forming a desired structure in the wafer, and forming an end structure in the wafer, said end structure extending to a greater depth, toward the back side of the wafer, than the desired structure. Also, the removing step includes the step of removing said substrate only to the end structure, whereby no part of the desired structure is removed during the removing step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.