Methods of compensating for an alignment error during fabrication of structures on semiconductor substrates
US7498248B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2006 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Aug 25, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70633
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
In the methods of compensating for an alignment error during fabrication of structures on semiconductor substrates, a conductive pattern structure is formed at a first position on a first semiconductor substrate. The conductive pattern structure includes a grid of first and second conductive patterns arranged as columns and intersecting rows with openings bounded therebetween. A first conductive contact structure overlaps the conductive pattern structure, and includes a plurality of spaced apart conductive contacts arranged as a grid of rows and columns that can be tilted at a non-zero angle relative to the grid of the conductive pattern structure. A determination is made as to whether the first conductive contact structure is electrically connected to the conductive pattern structure. A second conductive contact structure is formed at a position on a second semiconductor substrate that is determined in response to the determination of whether the first conductive contact structure is electrically connected to the conductive pattern structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.