Epitaxial silicon growth
US7498265B2 · kind B2 · utility
27Cited by
8References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2006 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Nov 25, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6211
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon growth. The method includes providing a silicon layer on a substrate. A dielectric layer is provided on the silicon layer. A trench is formed in the dielectric layer to expose the silicon layer, the trench having trench walls in the <100> direction. The method includes epitaxially growing silicon between trench walls formed in the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.