Semiconductor memory
US7498637B2 · kind B2 · utility
116Cited by
5References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2005 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Jun 10, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A SRAM memory is composed of FD-SOI transistors, and performance of the memory cell is improved by controlling an electric potential of a layer under a buried oxide film of a SOI transistor constituting a driver transistor. Performance of the SRAM circuit in the low power voltage state is improved. In the SRAM memory cell composed of the FD-SOI transistor, an electric potential of a well under a BOX layer is controlled to control a threshold voltage Vth, thereby increasing a current. Thus, the operations of the memory cell can be stabilized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.