Phase error correction circuit for a high speed frequency synthesizer
US7498852B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2007 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Mar 15, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuits, methods, and apparatus for adjusting an NCO output in order to provide a signal that is phase-locked to a reference signal. This is particularly beneficial where the frequencies of the NCO output and reference signal are unrelated. One embodiment provides a circuit that corrects the phase of the NCO output in two steps in order to reduce the chance of metastability. During the first, the output of the NCO is phase shifted to the closest correct portion of a cycle of a clock signal. A second correction is then performed by steering a number of currents under the control of at least some of a number of remainder bits from the NCO. The current steering provides a die area efficient, low-noise phase correction. The decoded remainder bits are latched using a feed forward circuit that prevents the device from entering a locked state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.