Fast, stable, SRAM cell using seven devices and hierarchical bit/sense line
US7499312B2 · kind B2 · utility
17Cited by
25References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2007 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Jun 9, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention is an SRAM memory array comprising memory cells with each cell containing seven devices, wherein the basic storage nodes, which store the true and complement of the data, are constructed from six devices, forming a cross-coupled flip-flop cell. One internal storage node of this cell being connected to a separate read-pass device which passes the state of this node to a local bit line (LBL) for single-ended sensing, with the gate of this separate read-pass device connected to a separate read-word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.