Method and apparatus for discharging a memory cell in a memory device after an erase operation
US7499334B2 · kind B2 · utility
0Cited by
10References
22Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 18, 2006 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Dec 24, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for discharging a memory cell in a memory device. In one implementation, the memory cell includes a capacitor having a first plate and a second plate, and the method includes initially discharging the first plate of the capacitor through a first discharge circuit and discharging the second plate of the capacitor through a second discharge circuit. After the initial discharge, the method further includes completely discharging the first plate of the capacitor and the second plate of the capacitor by coupling both the first plate of the capacitor and the second plate of the capacitor to ground.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.