Method and apparatus for providing frequency synthesis and phase alignment in an integrated circuit
US7499513B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2005 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Mar 16, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/095
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
According to particular example embodiments, an integrated circuit includes one or more serializing data transmitters. Each such data transmitter is arranged to transmit data on a respective data output port of the integrated circuit, wherein the respective data output port for at least one of the data transmitters is dedicated to transmitting periodic data used for clocking a respective target circuit. In other particular embodiments involving feedback, phase-locked loop (PLL) signal control and/or delay-locked loop (DLL) signal control is achieved in functional blocks of a programmable logic device (PLD). The PLD is responsive to a source clock and includes a configurable logic array that includes configurable logic blocks and configurable routing blocks, and the respective data output port for at least one of the data transmitters provides a respective target clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.