Hardware stack structure using programmable logic
US7500060B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2007 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Mar 16, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/785
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware stack (HSTACK) structure using programmable logic can include a look-up table (LUT) random access memory (RAM) circuit and circuitry within the LUT RAM circuit for propagating data upwards and downwards. The hardware structure can be arbitrarily assembled into a larger structure by adding stacks to a top portion, a bottom portion, or a portion between the top portion and the bottom portion. The hardware stack structure can further include a virtual stack (VSTACK) structure coupled to the HSTACK structure within a field programmable gate array (FPGA) fabric. The VSTACK can be arranged in the form of an appended peripheral memory and cache control for virtual extension to an HSTACK address space. The hardware stack structure can further include an auxiliary reset circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.