Apparatus and method for scheduling threads in multi-threading processors
US7500240B2 · kind B2 · utility
11Cited by
13References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 15, 2002 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | May 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An multi-threading processor is provided. The multi-threading processor includes a first instruction fetch unit to receive a first thread and a second instruction fetch unit to receive a second thread. A multi-thread scheduler coupled to the instruction fetch units and a execution unit. The multi-thread scheduler determines the width of the execution unit and the execution unit executes the threads accordingly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.