Method of making semiconductor BGA package having a segmented voltage plane
US7501313B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2006 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Dec 1, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device assembly and method of making the device are disclosed. The assembly comprises a semiconductor die attached to an electrically conductive layer, which is, in turn, connected to a dielectric layer carrying conductive traces of the electrical connection layer. The conductive traces provide connection between an array of discrete conductive elements and bonding wires connected to bond pads of the die. The conductive layer enhances thermal conduction and structural stiffness for the assembly. In addition, the conductive layer provides a voltage reference plane that may be connected to a power source, a ground source, or an intermediate reference voltage. The conductive layer also includes at least one electrical current isolation slot, which segments the conductive layer to help isolate noise induced in one segment of the conductive layer from the other segments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.