Interconnect array formed at least in part with repeated application of an interconnect pattern
US7501341B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 5, 2005 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Sep 23, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interconnect array formed at least in part using repeated application of an interconnect pattern is described. The interconnect pattern has at least ten interconnect locations. One of the ten interconnect locations is for a power interconnect. Another one of the ten interconnect locations is for a ground interconnect. At least eight interconnect locations remaining are for additional interconnects. The at least eight remaining interconnect locations disposed around a medial region, where either the ground interconnect or the power interconnect is located in the medial region. An offset region having the one of either the ground interconnect or the power interconnect not in the medial region. The interconnect array is at least partially formed by repeated application of the interconnect pattern off-set from one another responsive to the offset region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.