Semiconductor memory devices having contact pads with silicide caps thereon
US7501668B2 · kind B2 · utility
5Cited by
14References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2006 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Nov 9, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device having a semiconductor substrate includes a gate structure on the semiconductor substrate. Source/drain regions are on opposite sides of the gate structure. A contact pad is on at least one of the source/drain region, and a silicide cap is on a surface of the contact pad opposite the respective source/drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.