High density semiconductor memory
US7501676B2 · kind B2 · utility
26Cited by
16References
44Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 25, 2005 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Mar 25, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
Abstract
A memory cell, array and device include cross-shaped active areas and polysilicon gate areas disposed over arm portions of adjacent cross-shaped active areas. The polysilicon gate areas couple word lines with capacitors associated with each arm portion of the cross-shaped active areas. Buried digit lines are coupled to body portions of the cross-shaped active areas. The word lines and digit lines provide a unique contact to each capacitor of the array of memory cells. Each memory cell has an area of 5F2. An electronic system and method for fabricating a memory cell are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.