SONOS memory with inversion bit-lines
US7501677B2 · kind B2 · utility
4Cited by
2References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2006 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Apr 12, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0475
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A SONOS memory cell, formed within a semiconductor substrate, includes a bottom dielectric disposed on the semiconductor substrate, a charge trapping material disposed on the bottom dielectric, and a top dielectric disposed on the charge trapping material. Furthermore, the SONOS memory cell includes a word-line gate structure disposed on the top dielectric and at least one bit-line gate for inducing at least one inversion bit-line within the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.