Method and circuit for the detection of solder-joint failures in a digital electronic package
US7501832B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2006 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Jul 24, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/312
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The solder-joint integrity of digital electronic packages, such as FPGAs or microcontrollers that have internally connected input/output buffers, is evaluated by applying a time-varying voltage through one or more solder-joint networks to charge a charge-storage component. Each network includes an I/O buffer on the die in the package and a solder-joint connection, typically one or more such connections inside the package and between the package and a board. The time constant for charging the component is proportional to the resistance of the solder-joint network, hence the voltage across the charge-storage component is a measurement of the integrity of the solder-joint network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.