Voltage margining with a low power, high speed, input offset cancelling equalizer
US7501863B2 · kind B2 · utility
3Cited by
2References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2007 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Mar 30, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/005
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A switched-capacitor circuit that may be used for equalization, but configurable for voltage margining. The switched-capacitor circuit cancels the offset voltage inherent in an amplifier and sets the common mode of an input signal at half the rail voltage. Two capacitors level shift an input signal before being applied to the two input ports of an amplifier. When used for voltage margining, the input voltage swing is reduced at the input ports of the amplifier by connecting a digital-to-analog controlled voltage source to the two capacitors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.