Semiconductor device
US7502257B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2007 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Aug 27, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.