Clock frequency doubler method and apparatus for serial flash testing
US7502267B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2006 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Dec 11, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for memory device testing at a higher clock rate than the clock rate provided by a memory tester. The method includes providing a memory tester capable of generating a first clock signal characterized by a first clock frequency, and applying the first clock signal to the memory device. The method also includes receiving a command for activating a high-clock-frequency test mode. The method generates a second clock signal in the memory device in response to the first clock signal. The second clock signal is characterized by a second clock frequency which is higher than the first clock frequency. The method then tests the memory device at the second clock frequency. In a specific embodiment, the method is applied to a serial flash memory device. The invention can also be applied to testing and operating other memory devices or systems that include synchronized circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.