Semiconductor memory device
US7502275B2 · kind B2 · utility
172Cited by
9References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 23, 2006 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | May 23, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.