Word-line driver design for pseudo two-port memories
US7502277B2 · kind B2 · utility
15Cited by
7References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2006 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Nov 15, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention discloses an integrated circuit, which comprises a first and a second pull-down circuit controlled by a first and second signal, respectively, and coupled between a first node and a low voltage power supply (Vss), and a controllable pull-up circuit coupled between the first node and a complimentary high voltage power supply (Vcc), wherein when either the first or second signal is asserted to a predetermined logic state, the first node is pulled down to a logic LOW state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.