Sideband scout thread processor for reducing latency associated with a main processor
US7502910B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 28, 2003 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Apr 6, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sideband scout thread processing technique is provided. The sideband scout thread processing technique utilizes sideband information to identify a subset of processor instructions for execution by a scout thread processor. The sideband information identifies instructions that need to be executed to “warm-up” a cache memory that is shared with a main processor executing the whole set of processor instructions. Thus, the main processor has fewer cache misses and reduced latencies. In one embodiment, a system includes a first processor for executing a sequence of processor instructions, a second processor for executing a subset of the sequence of processor instructions, and a cache shared between the first processor and the second processor. The second processor includes sideband circuitry configured to identify the subset of the sequence of processor instructions to execute according to sideband information associated with the sequence of processor instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.