Methods for fabricating an integrated circuit

US7504287B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Sven Beyer · Dresden, DE
• Kamatchi Subramanian · Poughkeepsie, US

Key dates

• Filing date: Mar 22, 2007
• Grant date: Mar 17, 2009
• Expiry date: Mar 22, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/02362
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method is provided for fabricating a semiconductor device which includes a first contact point and a second contact point located above the first contact point. A first material layer is conformally deposited over the contact points, and a second material layer is deposited. A photoresist layer is applied and patterned to leave remaining portions. The remaining portions are trimmed to produce trimmed remaining portions which overlie eventual contact holes to the contact points. Using the trimmed remaining portions as an etch mask, exposed portions the second material layer are etched away to leave sacrificial plugs. The sacrificial plugs are etched away to form contact holes that reach portions the first material layers. Another etching step is performed to extend the contact holes to produce final contact holes that extend to the contact points.