Enhancement mode GaN FET with piezoelectric gate
US7504679B2 · kind B2 · utility
2Cited by
1References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 20, 2007 |
| Grant date | Mar 17, 2009 |
| Priority date | — |
| Expiry date | Aug 6, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
Abstract
One or more enhancement mode GaN devices has a stress-reduced gate region which interrupts the normally conductive 2Deg layer. A piezoelectric film is disposed over the stress-reduced gate region and can be excited to deflect and apply a stress to the stress reduced gate region to reintroduce the conductive 2Deg layer in that region and to turn on the device. A depletion mode segment may also be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.