Striped on-chip inductor
US7504705B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2006 |
| Grant date | Mar 17, 2009 |
| Priority date | — |
| Expiry date | Apr 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.