Interconnect structure to reduce stress induced voiding effect
US7504731B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 2, 2007 |
| Grant date | Mar 17, 2009 |
| Priority date | — |
| Expiry date | May 2, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.