Method and apparatus to create an erase disturb on a non-volatile static random access memory cell
US7505303B2 · kind B2 · utility
16Cited by
3References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2006 |
| Grant date | Mar 17, 2009 |
| Priority date | — |
| Expiry date | Aug 29, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C14/0063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for disturbing an erased memory location structure in a non-volatile portion of a semiconductor memory is disclosed. The present invention applies a voltage to a first memory location of a non-volatile portion of the semiconductor memory that is in a programmed state and a second memory location of a non-volatile portion of the semiconductor memory that is in an erased state so as to keep the first memory location programmed and to transition the second memory location from a programmed state to an erased state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.